The present invention relates to a semiconductor device having a barrier film formed to prevent the entry of moisture and a method of manufacturing the same and, more particularly, to a semiconductor device which prevents an overhang of a barrier film on the side wall of a contact hole after etching, and a method of manufacturing the same.
In the conventional process of manufacturing a semiconductor device such as a scaled MOS (Metal Oxide Semiconductor) transistor, secondary slow trapping occurs. Slow trapping is a phenomenon in which Vt characteristics and the like of a transistor change with time owing to the moisture contained in an interlevel insulating film. Slow trapping is described in detail in M. Noyori et al, "Secondary slow trapping--A new moisture induced instability phenomenon in scaled CMOS devices", 20th Ann. Proc. International Reliability Physics Symposium, pp. 113-121, 1982.
In a conventional semiconductor device, a film exhibiting good barrier properties with respect to moisture, e.g., a nitride film, is formed on a silicon substrate to prevent the entry of moisture so as to suppress slow trapping.
Some restrictions are imposed on an area in which this barrier film is formed. FIG. 2 shows a conventional semiconductor device having a barrier film formed on its surface after the interconnection step is complete. Referring to FIG. 2, gate polysilicon 9, an LDD side wall oxide film 9b, and a field oxide film 10 are selectively formed on a silicon substrate 1. A first interconnection 32, a second interconnection 42, a third interconnection 52, and a fourth interconnection 62 are sequentially formed on the silicon substrate 1, on which the gate polysilicon 9 and the like have been formed, through interlevel insulating films 33, 43, and 53. The first to fourth interconnections 32, 42, 52, and 62 are connected to each other through a contact hole 21, a first through hole 31, a second through hole 41, and a third through hole 51. A cover film 63 is formed on the fourth interconnection 62 and the interlevel insulating film 53 and a nitride film 3 serving as a barrier film is formed on the cover film 63.
When the multilevel interconnection structure shown in FIG. 2 is used, as is apparent from FIG. 2, the underlying interlevel film 4, the interlevel insulating films 33, 43, and 53, and the cover film 63 are deposited thick. For this reason, even if the nitride film 3 is formed on the surface of the semiconductor device, slow trapping is caused by the moisture contained in the underlying interlevel film 4 and the interlevel insulating films 33, 43, and 53. In order to prevent slow trapping, the nitride film 3 must be formed as closer to the surface of the silicon substrate 1 as possible.
FIG. 3 shows a conventional semiconductor device having a barrier film formed immediately after a transistor is formed. Referring to FIG. 3, gate polysilicon 9, a gate oxide film 9a, an LDD side wall oxide film 9b, and a field oxide film 10 are selectively formed on a silicon substrate 1. A nitride film 3 serving as a barrier film is formed on the silicon substrate 1 including the gate polysilicon 9 and the oxide films 9a, 9b, and 10. An underlying interlevel film 4 is formed on the nitride film 3. That is, no interlevel insulating film is present between the silicon substrate 1 and the nitride film 3. For this reason, no slow trapping is caused by the moisture contained in an interlevel insulating film.
In this structure, however, since the nitride film 3 is directly formed on the source/drain diffusion layer area of the silicon substrate 1, stress is produced in the nitride film 3 or energy levels and the like appear at the silicon interface, resulting in an increase in leakage current.
In order to solve these problems, the structure of the semiconductor device disclosed in Japanese Patent Laid-Open No. 2-158132 has been proposed. FIG. 4 shows the semiconductor device disclosed in this reference. An underlying oxide film 2 is formed on a silicon substrate 1 after a transistor is formed, and a nitride film 3 serving as a barrier film is formed on the underlying oxide film 2. By forming the underlying oxide film 2 between the silicon substrate 1 and the nitride film 3, the stress in the nitride film 3 can be reduced.
In the semiconductor device shown in FIG. 4, however, the following serious problem is posed. This problem will be described in detail with reference to FIGS. 5A to 5G showing the steps in manufacturing the semiconductor device in FIG. 4.
As shown in FIG. 5A, the underlying oxide film 2 having a thickness of 100 to 2,000 .ANG. is formed on the silicon substrate 1 to reduce the stress in the barrier film. The nitride film 3 having a thickness of 50 to 500 .ANG. is formed on the underlying oxide film 2 to prevent the entry of moisture. An underlying interlevel film 4 having a thickness of 8,000 to 15,000 .ANG. is formed on the nitride film 3 to flatten the surface of the semiconductor device.
As shown in FIG. 5B, a contact hole 5 is formed through the underlying interlevel film 4, the nitride film 3, the underlying oxide film 2.
As shown in FIG. 5C, a protective film 6 is formed on a portion of the underlying interlevel film 4 which is located around the contact hole 5 and in the contact hole 5. This protective film 6 prevents the occurrence of a leakage current due to lattice defects on the surface of the silicon substrate 1 when a dopant is implanted into the silicon substrate 1 to obtain good ohmic contact. Note that an n-type dopant is implanted into the contact hole on an n-type diffusion area, and a p-type dopant is implanted into the contact hole on a p-type diffusion area.
The protective film 6 is formed to have a thickness of 100 to 300 .ANG. by CVD (Chemical Vapor Deposition). However, since the coverage of a plasm CVD oxide film is not very good, the protective film 6 formed on the side wall of the contact hole 5 becomes thinner toward the bottom portion of the contact hole 5.
As shown in FIG. 5D, the protective film 6 on the underlying interlevel film 4 and the bottom surface of the contact hole 5 is removed by anisotropic etching. At this time, a spontaneous oxide film (not shown) is formed on the bottom surface of the contact hole 5, i.e., a portion of the silicon substrate 1 which is located in the contact hole 5.
As shown in FIG. 5E, oxide film wet etching is performed to remove the spontaneous oxide film in the contact hole 5. More specifically, etching is performed for about 30 seconds using a solution having a composition ratio of HF:NH.sub.4 F=1:30 with 5% NHF.sub.2 as an etchant. As a result, the contact resistance can be decreased.
At this time, as shown in FIG. 5D, the protective film 6 is hardly formed on the bottom portion of the side wall of the contact hole 5, and the nitride film 3 is not etched by oxide film wet etching. For this reason, as shown in FIG. 5E, the underlying interlevel film 4 and the underlying oxide film 2 are etched to form an overhang 3a of the nitride film 3. Note that if etching is performed for 30 seconds, the overhang 3a has a protrusion amount of about 300 .ANG..
As shown in FIG. 5F, a barrier metal 7 is formed on a portion of the underlying interlevel film 4 which is located around the contact hole 5 and in the contact hole 5 by sputtering. This barrier metal 7 prevents a reaction between the silicon substrate 1 and an interconnection metal or the like formed in the contact hole 5 afterward.
Since the overhang 3a is formed in the contact hole 5, the barrier metal 7 is not sufficiently sputtered on a portion 3b under the overhang 3a. As a result, a portion of the silicon substrate 1 is exposed.
As shown in FIG. 5G, an interconnection metal 8 is formed on a portion of the barrier metal 7 which is located around the contact hole 5 and in the contact hole 5. At this time, the silicon substrate 1 is partly exposed at the portion 3b because of insufficient sputtering of the barrier metal 7, and the interconnection metal 8 is in direct contact with the silicon substrate 1. Therefore, the interconnection metal 8 and the silicon substrate 1 react with each other when annealing or the like is performed. If, for example, the material for the interconnection metal 8 is aluminum or an aluminum alloy, this metal reacts with the silicon substrate 1 to form alloy spikes, resulting in a leakage current.
Assume that a buried metal 8' is formed by using tungsten (W) generated by a vapor phase reaction of WF.sub.4 gas instead of the interconnection metal 8 in FIG. 5G. In this case, fluorine (F) in the WF.sub.4 gas reacts with the silicon substrate 1 to form a recess 3c in the portion below the overhang 3a formed on the bottom portion of the contact hole 5, resulting in a leakage current.
As semiconductor devices become smaller in size and higher in integration degree, the contact size becomes smaller, and the aspect ratio of each contact increases. It is therefore expected that the coverage on the bottom portion of a contact will deteriorate according to the conventional sputtering techniques. For this reason, sputtering with a larger vertical sputter component, such as long sputtering or collimate sputtering, will dominate the future sputtering techniques. In this case, if the overhang 3a is formed on the side wall of the contact hole 5, the influence of the shadow portion formed on the silicon substrate 1 owing to the overhang 3a becomes stronger.